CIS655/CSE661: Advanced Computer Architecture
Instructor: Yuzhe (Richard) Tang
Textbook
Computer Architecture: A Quantitative Approach, 5th Edition, The Morgan Kaufmann Series in Computer Architecture and Design
Lecture schedule
| Topic | Session | Chapter | Slides |
|---|---|---|---|
| 1.Overview | intro | 1 | [link to BB] |
| 1.Overview | metrics | 1 | [link to BB] |
| 2.CPU | ILP & pipelining | A | [link to BB] |
| 2.CPU | data hazard by compiler | 3 | [link to BB] |
| 2.CPU | branch hazard by HW | C.2,3.3,3.9 | [link to BB] |
| 2.CPU | data hazard by HW, a.k.a tomasulo | 3.4,3.5,3.6,3.9 | [link to BB] |
| 2.CPU | multi-issue & SIMD | 3 | [link to BB] |
| 3.Memory | cache | 2.1,2.2,B.1,B.2,B.3 | [link to BB] |
| 3.Memory | cache2 | 2.2 | [link to BB] |
| Mid-term covers till here | |||
| 3.Memory | memory | B.4,B.5,2.4 | [link to BB] |
| 3.Memory | memory protection | B.4,B.5,2.4 | [link to BB] |
| 4.Multi-processing | multiprocessing | 5.1,5.2 | [link to BB] |
| 4.Multi-processing | cache-coherence | 5.2,5.3,5.4 | [link to BB] |
| 4.Multi-processing | synchronization | 5.5 | [link to BB] |
| 4.Multi-processing | memory consistency | 5.5, 5.6 | [link to BB] |
| 4.Multi-processing | many-core | 5.8 | [link to BB] |
| 5.IO | storage | D | [link to BB], [one more] |
| 5.IO | raid & lsm | D | [link to BB] |
| 5.IO | interconnect | F | [link to BB] |
| 6.WSC | wsc | 6 | [link to BB] |
| 6.WSC | energy | 6 | [link to BB] |
| review | [link to BB] |